Seismic surveillance instruments
For: the New Zealand Seismological Observatory
This project culminated in the re-equipment of the New Zealand Seismic Network with digital instruments built in-house. Dr Randall advocated the project, demonstrated the feasibility and took on the whole process from initial concept through detailed design, pcb layout, prototype assembly, debugging and testing. A colleague with considerable analog skills joined the team and together we enjoyed a successful outcome. We made a particular effort to incorporate testability of both the digital logic and the firmware. Successful designs included:
- A 6802 microprocessor based seismic surveillance system, including fm telemetry discriminators, test equipment to facilitate their alignment, and a multi-channel display controller.
- A 68701 microprocessor based interface between a DEC computer (RS232) and a Wang flatbed plotter (proprietary parallel).
- An interface to a photo-typesetting machine for the Government Printer to facilitate Hansard production.
- A 6809 microprocessor based seismic network data recording system under contract to NZEC.
- A dual-processor (68000 and 6809) target software development and test system. The processors were loosely coupled via dual-ported RAM and ran on separate buses with the capability to interrupt each other. Either could be in control, using the other as an intelligent IO processor (6809) or 32-bit co-processor (68000).
- An HCMOS HM6309 based digital recording system for geophysical data acquisition. This highly successful instrument replaced photographic recorders throughout the NZ seismological network and has attracted favourable international interest. This modular flexible system included the following boards of our design:
- CPU, with main system processor, RAM, ROM, RS232 IO and bus interface logic.
- MEMORY, configurable for varying proportions of RAM/ROM.
- CLOCK, accurate time-keeping, with NVRAM for parameter storage.
- PARALLEL IO for analog bus configuration and printer interface.
- DUAL RING-BUFFER, a delayed data interface with the Storage Processor.
- STORAGE PROCESSOR, a loosely coupled 2nd processor board to control data storage to (1) CIPHER tape and (2) various SCSI devices.
- TIME-PIP DETECTOR for synchronizing the clock using radio time signals.
- Also boards to facilitate software development using the target processor itself, and the development of a suite of test software for board qualification at the production stage: "silicon disk" , floppy and SCSI hard disk controllers.
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